Category: HPC

Methodology of Firmware Development for ARUZ — An FPGA-Based HPC System,

Methodology of Firmware Development for ARUZ — An FPGA-Based HPC System

ARUZ, HPC February 1, 2021 Journal: MDPI Electronics Publication date: 10 September 2020 DOI: 10.3390/electronics9091482 Access type: Open Access (direct link) Link: http://dx.doi.org/10.3390/electronics9091482   Abstract ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a...
IP core for MPA computations,

IP core for MPA computations

HPC, SRUP February 1, 2021 Conference: 2018 MIXDES - 25th International Conference "Mixed Design of Integrated Circuits and Systems" Publication date: 22 June 2018 DOI: 10.23919/MIXDES.2018.8436868 Access type: Paid Access (IEEE Xplore) Link: https://dx.doi.org/10.23919/MIXDES.2018.8436868   Abstract In this paper, we present an IP core of coprocessor...
FPGA implementation of the multiplication operation in multiple-precision arithmetic,

FPGA implementation of the multiplication operation in multiple-precision arithmetic

HPC, SRUP February 1, 2021 Conference: 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems" Publication date: 23 June 2017 DOI: 10.23919/MIXDES.2017.8005214 Access type: Paid Access (IEEE Xplore) Link: https://dx.doi.org/10.23919/MIXDES.2017.8005214   Abstract Although standard 32/64-bit arithmetic is sufficient to solve most...
ARUZ — Large-scale, massively parallel FPGA-based analyzer of real complex systems,

ARUZ — Large-scale, massively parallel FPGA-based analyzer of real complex systems

ARUZ, HPC January 30, 2021 Journal: Computer Physics Communications Publication date: 1 November 2018 DOI: 10.1016/j.cpc.2018.06.010 Access type: Paid Access (Elsevier) Link: https://doi.org/10.1016/j.cpc.2018.06.010   Abstract This paper presents general information about ARUZ, a scalable, fully parallel data processing system equipped with low-latency communication channels, designed for simulations of...
From the Dynamic Lattice Liquid Algorithm to the Dedicated Parallel Computer – mDLL Machine,

From the Dynamic Lattice Liquid Algorithm to the Dedicated Parallel Computer – mDLL Machine

HPC, mDLL January 30, 2021 Journal: Computational Methods in Science and Technology Publication date: 24 December 2018 DOI: 10.12921/cmst.2018.0000054 Access type: Open Aceess (direct link) Link: http://dx.doi.org/10.12921/cmst.2018.0000054   Abstract The designing, production and testing of the mDLL machine led to the development of such a...
Od algorytmu dynamicznej cieczy sieciowej do dedykowanego komputera równoległego II – maszyna mDLL,

Od algorytmu dynamicznej cieczy sieciowej do dedykowanego komputera równoległego II – maszyna mDLL

HPC, mDLL January 30, 2018 Journal: Przegląd Elektrotechniczny Publication date: 1 November 2017 DOI: 10.15199/48.2017.11.34 Access type: Paid Access (SIGMA-NOT) Link: https://doi.org/10.15199/48.2017.11.34   Abstract W artykule opisano złożenia projektowe, budowę i realizację maszyny przeznaczonej do symulacji zjawisk zachodzących w wieloskładnikowych układach molekularnych. Przedstawiony system elektroniczny...