contact@brightelligence.com +48 888 888 351

Category: HPC

Parallel model of chemical reactions on a grained molecular level,

Parallel model of chemical reactions on a grained molecular level

ARUZ, HPC August 2, 2023 Journal: Computer Physics Communications Publication date: 2 August 2023 DOI: 10.1016/j.cpc.2023.108884 Access type: Open access (direct link) Link: http://dx.doi.org/10.1016/j.cpc.2023.108884   Abstract In this paper, the model of chemical reactions on grained molecular level is presented. This model allows simulating simple...
Simulation of diffusion in dense molecular systems on ARUZ – Massively-parallel FPGA-based machine,

Simulation of diffusion in dense molecular systems on ARUZ – Massively-parallel FPGA-based machine

ARUZ, HPC November 11, 2022 Journal: Computer Physics Communications Publication date: 11 November 2022 DOI: 10.1016/j.cpc.2022.108591 Access type: Paid (Elsevier) Link: http://dx.doi.org/10.1016/j.cpc.2022.108591   Abstract In this paper, the implementation of a molecular diffusion model named Dynamic Lattice Liquid (DLL) is discussed. Two algorithms, sequential and parallel, implementing this model...
Molecular Diffusion Simulation on ARUZ – Massively-parallel FPGA-based Machine,

Molecular Diffusion Simulation on ARUZ – Massively-parallel FPGA-based Machine

ARUZ, HPC July 30, 2021 Journal: 2021 28th International Conference on Mixed Design of Integrated Circuits and System Publication date: 30 lipca 2021 DOI: 10.3390/electronics9091482 Access type: Paid (IEEEXplorer) Link: http://dx.doi.org/10.23919/MIXDES52406.2021.9497622   Abstract In this paper, the implementation of a molecular diffusion model named Dynamic...
Methodology of Firmware Development for ARUZ — An FPGA-Based HPC System,

Methodology of Firmware Development for ARUZ — An FPGA-Based HPC System

ARUZ, HPC September 10, 2020 Journal: MDPI Electronics Publication date: 10 September 2020 DOI: 10.3390/electronics9091482 Access type: Open Access (direct link) Link: http://dx.doi.org/10.3390/electronics9091482   Abstract ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a...
Open-Source Coprocessor for Integer Multiple Precision Arithmetic,

Open-Source Coprocessor for Integer Multiple Precision Arithmetic

HPC, SRUP July 20, 2020 Journal: MDPI Electronics Publication date: 14 lipca 2020 DOI: 10.3390/electronics9091482 Access type: Open Access (bezpośredni link) Link: http://dx.doi.org/10.3390/electronics9071141   Abstract This paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor...
From the Dynamic Lattice Liquid Algorithm to the Dedicated Parallel Computer – mDLL Machine,

From the Dynamic Lattice Liquid Algorithm to the Dedicated Parallel Computer – mDLL Machine

HPC, mDLL December 24, 2018 Journal: Computational Methods in Science and Technology Publication date: 24 December 2018 DOI: 10.12921/cmst.2018.0000054 Access type: Open Aceess (direct link) Link: http://dx.doi.org/10.12921/cmst.2018.0000054   Abstract The designing, production and testing of the mDLL machine led to the development of such a...
ARUZ — Large-scale, massively parallel FPGA-based analyzer of real complex systems,

ARUZ — Large-scale, massively parallel FPGA-based analyzer of real complex systems

ARUZ, HPC November 1, 2018 Journal: Computer Physics Communications Publication date: 1 November 2018 DOI: 10.1016/j.cpc.2018.06.010 Access type: Paid Access (Elsevier) Link: https://doi.org/10.1016/j.cpc.2018.06.010   Abstract This paper presents general information about ARUZ, a scalable, fully parallel data processing system equipped with low-latency communication channels, designed for simulations of...
IP core for MPA computations,

IP core for MPA computations

HPC, SRUP June 22, 2018 Conference: 2018 MIXDES - 25th International Conference "Mixed Design of Integrated Circuits and Systems" Publication date: 22 June 2018 DOI: 10.23919/MIXDES.2018.8436868 Access type: Paid Access (IEEE Xplore) Link: https://dx.doi.org/10.23919/MIXDES.2018.8436868   Abstract In this paper, we present an IP core of coprocessor...
Od algorytmu dynamicznej cieczy sieciowej do dedykowanego komputera równoległego II – maszyna mDLL,

Od algorytmu dynamicznej cieczy sieciowej do dedykowanego komputera równoległego II – maszyna mDLL

HPC, mDLL November 1, 2017 Journal: Przegląd Elektrotechniczny Publication date: 1 November 2017 DOI: 10.15199/48.2017.11.34 Access type: Paid Access (SIGMA-NOT) Link: https://doi.org/10.15199/48.2017.11.34   Abstract W artykule opisano złożenia projektowe, budowę i realizację maszyny przeznaczonej do symulacji zjawisk zachodzących w wieloskładnikowych układach molekularnych. Przedstawiony system elektroniczny...
FPGA implementation of the multiplication operation in multiple-precision arithmetic,

FPGA implementation of the multiplication operation in multiple-precision arithmetic

HPC, SRUP June 23, 2017 Conference: 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems" Publication date: 23 June 2017 DOI: 10.23919/MIXDES.2017.8005214 Access type: Paid Access (IEEE Xplore) Link: https://dx.doi.org/10.23919/MIXDES.2017.8005214   Abstract Although standard 32/64-bit arithmetic is sufficient to solve most...