FPGA engineering for projects where precision matters
Brightelligence delivers advanced FPGA design services for complex, performance-critical systems
– from architecture and RTL development to verification, timing closure, bring-up, debugging,
and rescue support.
Industries we support
Selected projects
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ARUZ: FPGA Computing at Extraordinary Scale
ARUZ is one of the defining projects in Brightelligence’s engineering history. It represents the kind of FPGA work that exists far beyond ordinary board design, RTL implementation, or subsystem integration. ARUZ was…
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ARCHYTAS – European Defence Fund Project
Brightelligence is a consortium partner in ARCHYTAS, a major European Defence Fund (EDF) research project focused on next-generation hardware architectures for dependable and energy-efficient AI systems in defence applications. The project reflects the type of advanced European…
Bright FPGA Academy
Turn Junior FPGA Engineers into Confident Mid-Level Professionals
A long-term, hands-on FPGA training programme for companies that want to develop junior engineers in a structured, practical, and measurable way without relying only on learning on the job.
Knowledge
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Od algorytmu dynamicznej cieczy sieciowej do dedykowanego komputera równoległego II – maszyna mDLL
Categories: HPC, mDLL Journal: Przegląd Elektrotechniczny Publication date: 15 November 2017 DOI: 10.15199/48.2017.11.34 Access type: open W artykule opisano złożenia projektowe, budowę i realizację maszyny przeznaczonej do symulacji zjawisk zachodzących w wieloskładnikowych układach molekularnych. -
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Do FPGA designers and hardware designers need to talk?
In the FPGA-oriented project there are two key roles in the design process: FPGA engineer and hardware designer. FPGA allows for the implementation of complex digital circuits in a single integrated circuit.…
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FPGA design debugging… How hard can it be?
Debugging in FPGA systems is a critical aspect of the development process due to the complexity and high-performance demands of FPGA designs. Unlike traditional software debugging, FPGA debugging involves both hardware and…
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Parallel model of chemical reactions on a grained molecular level
Categories: HPC, ARUZ Journal: Computer Physics Communications Publication date: 2 August 2023 DOI: 10.1016/j.cpc.2023.108884 Access type: open In this paper, the model of chemical reactions on grained molecular level is presented. -
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Molecular diffusion simulation on ARUZ – massively-parallel FPGA-based machine
Categories: HPC, ARUZ Conference: 2021 28th International MIXDES Conference Publication date: 30 July 2021 DOI: 10.23919/MIXDES52406.2021.9497622 Access type: paid (IEEE Xplore) In this paper, the implementation of a molecular diffusion model named Dynamic Lattice Liquid (DLL) is discussed. -
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Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System
Categories: HPC, ARUZ Journal: MDPI Electronics Publication date: 10 September 2020 DOI: 10.3390/electronics9091482 Access type: open This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. -
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Simulation of diffusion in dense molecular systems on ARUZ – Massively-parallel FPGA-based machine
Categories: HPC, ARUZ Journal: Computer Physics Communications Publication date: 11 November 2022 DOI: 10.1016/j.cpc.2022.108591 Access type: paid (Elsevier) In this paper, the implementation of a molecular diffusion model named Dynamic Lattice Liquid (DLL) is discussed. -
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FPGA implementation of the multiplication operation in multiple-precision arithmetic
Categories: HPC, MPA Conference: 2017 24th International MIXDES Conference Publication date: 10 August 2017 DOI: 10.23919/MIXDES.2017.8005214 Access type: paid (IEEEXplore) In this contribution, our implementation of the base case-multiplication algorithm in MPA on FPGA is presented. -
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The Hidden Tax of Bad FPGA Project Methodology
FPGA projects are often perceived as risky, slow, and difficult to predict. While tool complexity and device constraints are commonly blamed, the dominant factor behind missed deadlines and spiraling costs is methodology.…
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From the Dynamic Lattice Liquid Algorithm to the Dedicated Parallel Computer – mDLL Machine
Categories: HPC, mDLL Journal: Computational Methods in Science and Technology Publication date: 24 December 2018 DOI: 10.12921/cmst.2018.0000054 Access type: open The designing, production and testing of the mDLL machine led to the development of such a structure in which operational cells (e.g. KDLL) were located in the nodes of a three-dimensional torus network and the device was scalable. -
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ARUZ — Large-scale, massively parallel FPGA-based analyzer of real complex systems
Categories: HPC, ARUZ Journal: Computer Physics Communications Publication date: 18 June 2018 DOI: 10.1016/j.cpc.2018.06.010 Access type: paid (ScienceDirect) This paper presents general information about ARUZ, a scalable, fully parallel data processing system equipped with low-latency communication channels, designed for simulations of interactions among huge number of relatively simple elements. -
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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations
Categories: HPC, MPAConference: 2018 25th International Conference on Mixed Design of Integrated Circuits and SystemPublication date: 16 August 2018DOI: 10.23919 type: paid (IEEE Xplore)Link: Abstract In this paper, we present an IP core of coprocessor supporting computations…
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Overview of highly efficient design techniques for FPGA firmware development flow
The ever-growing demand for experienced FPGA engineers outpaces the reality of market supply. To sustain this trend, success hinges on higher efficiency. This new approach requires breaking away from some old habits…
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Building the largest FPGA array in the world. How hard can it be?
ARUZ, Polish abbreviation of “Analyzer of Real Complex Systems”, is a multi-purpose FPGA-based machine initially built for speeding up molecular chemistry simulations, which find use in several fields like pharmacy, chemical industry,…