FPGA implementation of the multiplication operation in multiple-precision arithmetic

HPC, SRUP February 1, 2021

Conference: 2017 MIXDES – 24th International Conference “Mixed Design of Integrated Circuits and Systems”

Publication date: 23 June 2017

DOI: 10.23919/MIXDES.2017.8005214

Access type: Paid Access (IEEE Xplore)

Link: https://dx.doi.org/10.23919/MIXDES.2017.8005214



Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows one to implement MPA algorithms in hardware. Whereas addition and subtraction operations of two n-digit numbers require O(n) operations, the basecase multiplication is equivalent to the convolution computation that requires O(n 2 ) operations. Therefore, an efficient implementation of the multiplication operation is crucial for application of the reconfigurable hardware in MPA computations. In this contribution, our implementation of the base case-multiplication algorithm in MPA on FPGA is presented. The method is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. In the developed implementation of the MPA multiplication, the multiplication of two integer 1024-bit numbers (2048-bit numbers) takes 205 nsec (819 nsec) with the use of 40 DSP modules. It gives two-fold speedup in comparison to the reference results published in the literature. The developed digital circuit of the MPA multiplier works with integer numbers of precision varying in the range between 16 bits and 32 kbits. Such a scalability allows one to use the developed method not only in scientific computing, but also in embedded systems employing encryption based on MPA.